Alpha 21264 Microprocessor — Out-of-Order 64-bit RISC

The Alpha 21264, known internally as EV6, was the third generation of the Alpha architecture and the first to execute instructions out of order. It combined a four-wide fetch engine, clustered integer execution, large on-chip caches and a new high-bandwidth system bus, and it was the processor at the heart of Alpha Processor, Inc.'s boards.

Background

The first two Alpha generations, the 21064 and 21164, won benchmarks largely through raw clock speed. Digital's designers ran simple in-order pipelines at frequencies well ahead of competing RISC chips. By the mid-1990s that approach was running out of room: memory latency was not improving as fast as clock rates, and in-order pipelines spent more and more time waiting for data. The 21264 changed course. It kept high frequencies but added aggressive out-of-order execution, so the chip could look past stalled instructions and keep its execution units busy.

The design was introduced by Digital in 1998, manufactured initially in a 0.35-micron CMOS process, with roughly fifteen million transistors. Samsung, one of the founding partners of Alpha Processor, Inc., became a key second source and volume manufacturer, and API sold the processor on Slot B modules for its own boards and for other integrators.

Microarchitecture

Front end

The 21264 fetches four instructions per cycle from its instruction cache. To keep that stream flowing, it uses a line and way predictor inside the cache and a sophisticated tournament branch predictor that combines a local history predictor, a global history predictor and a chooser that picks between them. This hybrid scheme was among the most accurate of its time and became a textbook example of branch prediction design.

Out-of-order engine

After decode, instructions are renamed onto a large pool of physical registers, roughly eighty integer and seventy-two floating-point, and placed into separate integer and floating-point issue queues. Up to around eighty instructions can be in flight at once. Each cycle the queues can issue up to six instructions, four integer and two floating-point, to whichever units are ready, regardless of program order. A reorder mechanism retires them in order, so precise exceptions are preserved.

Clustered integer units

One of the 21264's most distinctive features is its clustered integer design. Rather than build one very large register file with enough ports for four integer pipelines, which would have limited clock speed, the designers split the integer execution units into two clusters. Each cluster has its own copy of the integer register file. When a result is produced in one cluster it is available immediately there, but takes an extra cycle to reach the other. The issue logic is aware of this and tries to schedule dependent instructions on the same side. The trade-off, a small latency penalty for a much faster register file, was a major reason the chip could reach high frequencies despite its complexity.

Caches and memory system

The chip carries a 64 KB instruction cache and a 64 KB data cache on die, both two-way set associative, which was large for the era. The data cache is effectively dual-ported, allowing two loads per cycle. Behind the L1 caches sits an external backside L2 cache on a dedicated 128-bit data interface, running at a fraction of the core clock and typically sized from 2 MB to 8 MB on commercial modules. Keeping the L2 on its own bus meant cache traffic never competed with main memory or I/O.

The EV6 bus

The system interface was equally new. The EV6 bus is a point-to-point, source-synchronous link that transfers data on both clock edges, giving much higher bandwidth than traditional shared front-side buses. Each processor gets its own link to the chipset, which is what allowed multiprocessor Alpha boards such as the UP2000 to scale cleanly. Digital licensed this bus to AMD, which adopted it for the Athlon, a decision that later let API build the UP1000 around an Athlon chipset.

Main characteristics

Target workloads

The 21264's combination of high clock speed, deep out-of-order execution and a strong floating-point pipeline made it the processor of choice for a range of demanding applications:

• Scientific simulation, weather modelling and computational chemistry.
• Mechanical and electronic design automation.
• Rendering, visualisation and digital content creation.
• Large databases and 64-bit commercial applications on Tru64 UNIX and OpenVMS.
• Linux clusters, where price per floating-point operation mattered most.

Operating system and software support

On Compaq hardware the 21264 ran Tru64 UNIX and OpenVMS, both fully 64-bit and mature. Windows NT 4.0 for Alpha supported early 21264 systems, but Compaq cancelled NT development for Alpha in 1999, before Windows 2000 shipped. Linux supported the 21264 well, including Tsunami SMP systems, and that is where API concentrated its efforts. Compaq's optimising compilers for Linux on Alpha were widely used to extract the chip's full floating-point potential.

Position in the API line

API sold the 21264 on Slot B modules for its own boards and to third parties. It was succeeded by the 21264A (EV67), a die shrink that raised clock speeds and reduced power without changing the core design. See also the microprocessor overview.