API NetWorks Accelerates Use of HyperTransport Technology with Industry's 1st HyperTransport-to-PCI Bridge
API NetWorks today introduced what it describes as the industry's first HyperTransport-to-PCI bridge, a chip that connects a high-speed HyperTransport link to a conventional PCI bus so that equipment makers can adopt the new interconnect while continuing to use the enormous installed base of PCI devices and software.
CONCORD, Mass. — April 2, 2001 — API NetWorks, Inc. today announced its HyperTransport-to-PCI bridge, the first product in its planned family of HyperTransport interconnect devices. The bridge gives designers of networking equipment, servers, storage systems and embedded platforms a practical way to attach existing PCI controllers — network interfaces, storage adapters, graphics and custom logic — to a system built around HyperTransport links. The announcement follows API NetWorks' February 2001 commitment to support HyperTransport technology, which the company co-developed with AMD.
Why a bridge comes first
New interconnects succeed only when designers can use them without abandoning everything that came before. In 2001, virtually every peripheral chip on the market — Ethernet controllers, SCSI and Fibre Channel adapters, security processors, custom FPGAs — spoke PCI. A system designer attracted to HyperTransport's bandwidth and low pin count still needed to attach those parts. A bridge solves that problem: the processor or system controller talks HyperTransport, and the bridge presents one or more standard PCI buses to the rest of the board.
Because HyperTransport uses a PCI-compatible configuration model, the bridge can make the transition almost invisible to software. Operating systems enumerate the PCI devices behind the bridge in the usual way, and existing drivers continue to work. That combination of new hardware performance and old software compatibility is what makes the bridge the logical first product.
How the bridge works
On one side, the device implements a HyperTransport link that carries packets to and from the host at high speed using low-voltage differential signaling. On the other side, it drives a conventional parallel PCI bus. Internally it translates between the two protocols, buffering transactions, converting HyperTransport requests into PCI cycles and back again, and handling ordering rules so that data arrives consistently. It can also be used in chains of HyperTransport devices, contributing to larger I/O structures within a system.
| Feature | Description |
|---|---|
| Upstream interface | HyperTransport link using low-voltage differential signaling |
| Downstream interface | Standard PCI bus, with support for 64-bit operation |
| Software model | PCI-compatible configuration and enumeration |
| Transaction handling | Protocol translation with buffering and ordering control |
| Target markets | Networking, communications, servers, storage, embedded |
| Development support | Evaluation platforms and reference designs |
Specific link widths, clock rates and packaging details are covered in the product documentation available through API support.
Benefits for system designers
- Protect existing investment: keep using proven PCI peripherals and drivers while moving the system core to HyperTransport.
- Reduce pin count: a narrow HyperTransport link replaces a wide parallel bus at the host, simplifying board layout.
- Scale I/O: multiple bridges can provide multiple independent PCI buses, spreading peripheral load.
- Shorten time to market: evaluation hardware and reference designs let teams begin development immediately.
- Future-proof designs: as native HyperTransport peripherals appear, they can join the same fabric alongside bridged PCI devices.
Typical design scenarios
- A network router whose control processor uses HyperTransport, with PCI-attached line-card controllers behind the bridge.
- A server chipset that exposes HyperTransport and uses bridges to provide expansion slots.
- A storage appliance connecting several PCI host adapters to a HyperTransport-based controller.
- An embedded board combining a HyperTransport-capable processor with PCI-based custom logic.
HyperTransport is only as useful as the devices you can connect to it. A bridge to PCI means designers can start using the interconnect today, with the parts they already know.
An API NetWorks product manager
Building a HyperTransport ecosystem
The bridge is the first step in the strategy API NetWorks outlined earlier in 2001, which calls for bridges, switching and tunnel devices, reference platforms and engineering services. Each piece lowers the barrier for equipment makers considering HyperTransport. The company's experience designing high-speed Alpha systems, from motherboards such as the UP2000 to the dense CS20 server, is directly relevant: in both cases the engineering problem is moving large amounts of data between chips quickly and reliably.
It also illustrates how API NetWorks' business was evolving. While the company continued to support Alpha customers and partners, interconnect silicon offered a market not tied to any one processor architecture. A HyperTransport bridge could serve communications equipment, PCs and embedded systems alike.
About API NetWorks, Inc.
API NetWorks, Inc., formerly Alpha Processor, Inc., is headquartered in Concord, Massachusetts. The company was founded in 1998 as a joint effort of Samsung and Digital Equipment Corporation, later Compaq, to bring the 64-bit Alpha RISC architecture into mainstream markets. API designs and markets Alpha motherboards, processor modules, high-density rack servers and system-level building blocks for Linux and Tru64 UNIX, and supplies them to OEMs, system integrators and cluster builders worldwide. Through its API NetWorks unit the company is extending its high-performance design expertise into interconnect silicon and platforms for networking and communications equipment.